The age of completely monolithic processors is gradually coming to an end, as the ability of silicon technology to create such gigantic chips has also reached its limit. At the International Solid-State Circuits (ISSCC 2022) conference, both AMD and Intel shared some details about the internals of their new server processors: Milan-X and Sapphire Rapids . And the German portal Hardwareluxx told about the reports about both the first and the second .
And if AMD switched to a chiplet layout a long time ago, then for Intel this approach is new and, on the whole, forced – Sapphire Rapids in the classical implementation would require an unthinkable in size monolithic crystal, which would drastically reduce the yield of suitable products. However, the new Xeon already consist of four basic crystals with an area of about 400 mm 2 .
They are manufactured using the Intel 7 process (10 nm variation), which primarily allowed to increase the density of the interconnect, which is critical to achieve minimum latency between blocks in the assembly. Echoes with process problems still make themselves felt: although the base die of Sapphire Rapids is relatively small, Intel decided to play it safe and increase the degree of redundancy for some blocks.
In fact, the company produces two mirrored crystals that are connected by ten EMIB interfaces – either pairs (vertically) or triples (horizontally) of connections to the Multi-Die Fabric IO factory. The minimum consumption of this technology is only 0.5 J / byte, and the factory frequency can dynamically vary from 800 to 2500 MHz. The total throughput is 10 TB/s (20 × 500 GB/s), latency does not exceed 10 ns.
AMD, on the other hand, not only abandoned monolithic crystals, but also switched to an asymmetric chiplet layout from the second generation, in which the I / O crystal is not only separated from crystals with cores, but is also produced using a different manufacturing process (14 nm versus 7 nm). And in Zen 3 , caches were also compacted – 32 MB L3 for eight cores. The cores and cache are connected by a bidirectional ring bus with a bandwidth of 2 TB / s.
And the caches themselves switched to using more compact cells and acquired two rows of TSV connections for installing another 41 mm 2 SRAM chip using TSMC SoIC technology , that is, the same 3D V-Cache that allows you to increase the L3 capacity from 32 to 96 MB. Interestingly, the connection with the lower chip is carried out solely due to the adhesion of the copper pillars-conductors, soldering is not required. In fact, the already finished CCD die is simply polished to expose the TSV conductors, after which the top SRAM die is laid on it.
At the same time, CCDs themselves also received a number of “silicon” optimizations and some transformations in the structure. They are thinner and where additional SRAM is not required, shims are now used to equalize the height. And the same TSV conductors are also used to power the external SRAM chip. The total connection bandwidth of 3D V-Cache is the same 2 TB / s, and inside it is organized in blocks of 512 × 128 KB. But the main thing is that the “penalty” for accessing the extended cache memory should not exceed four cycles.
Both companies are looking for original solutions when creating new processors. But if Intel refuses solidity with some difficulty and in Sapphire Rapids the desire to maintain the highest possible level of connectivity within the CPU is clearly visible , then AMD seems to be playing LEGO. With access to TSMC’s advanced manufacturing processes, the Reds have the ability to comb through dice combinations in search of the design that best matches the company’s vision of the ideal processor.