Intel is going to create processors with more than a trillion transistors in less than 10 years.
At the IEDM 2022 event, the company published nine research papers on future developments and plans. In particular, it describes new 2D materials for transistors, a new 3D packaging technology that will reduce the performance and power gap between chiplets and single-chip processors to an almost imperceptible range, and so on. There is also information about Intel’s plans to release processors with more than a trillion transistors by 2030.
Intel is betting heavily on a new 3D packaging technology for Quasi-Monolithic Chips (QMC). The bottom line is that QMC aims to offer almost the same performance as interconnects used in monolithic chips. QMC is known to be a new sub-3 micron pitch hybrid interconnect technology that results in a 10x increase in power efficiency and performance density compared to Intel designs presented at last year’s IEDM. The 10 micron step approach was described last year, and even that was already a 10x improvement over current technologies. That is, Intel, at least on paper, was able to achieve a 100-fold improvement in energy efficiency and density in just a few years. In addition, QMC also allows multiple chips to be stacked vertically on top of each other.
Interestingly, the rate of increase in the density of transistors in the foreseeable future, according to Intel’s plans, will approximately correspond to Moore’s law. At the same time, prices for semiconductor products will continue to grow.